This invention relates to improvements in multi-segment communication networks, and more specifically to data terminal equipment including elastic buffers for absorbing phase error and phase drift (mismatched frequencies) between two segments of a communication network controlled by separate, mismatched, clocks operating at nominally identical frequencies. Still more particularly, the invention relates to such data terminal equipment including variable preload means for loading the buffer therein to selectable preload levels in order to minimize occurrences of underflow and overflow alarms and to such devices wherein an alarm circuit is available to a user for generating an alarm to one or the other of the two segments of the communication network.
Null data terminal equipment (DTE) is known for use in interfacing between two segments of a multi-segmented communication network. Such DTE's are typically connected between two data communications equipment (DCE) as illustrated at 10, 12 and 14 in FIG. 1. As shown therein, each DCE provides a "receive timing" (RT) signal to the DTE to control reception of data thereby. Similarly, each DCE provides a "send timing" (ST) signal to the DTE to request that the DTE send data to the DCE.
Thus, the DTE responds to an RT signal from one DCE to accept "received data" (RD) therefrom. Similarly, the DTE responds to the ST signal provided by the second DCE to transmit "send data" (SD) thereto. The DCE's are typically remotely located modems which transmit the ST and RT signals to DTE 10 over the segments of the communication network, which may be long line communication links of the telephone company, a satellite link, or other communications links. Where the DCE, or modems, of two segments of the network each have separate master clocks, timing errors frequently occur as a result of phase error and phase drift causing frequency mismatch.
Thus, in a communication link for two communication segments from two remotely connected modems, each having its own internal clock, the received data (RD) will be present at the output of the modem at DCE 12 in synchronism with the RT clock thereof. If the ST clock of DCE 14 is of the same frequency as (and is in phase with) RT of DCE 12, then RT from DCE 12 will be successfully clocked into the SD path of DCE 14. However, since the modems have their own individual internal clocks, typically the modems do not operate at exactly the same frequency with exactly the same stability.
Illustratively, if the clock rate for DCE 12 is 56,000 Hz, while that for DCE 14 is 56,001.5 Hz, with respective stabilities of .+-.1.5 Hz and .+-.0.5 Hz respectively, it is seen that DCE 14 has a faster ST clock than the RT clock of DCE 12. Under such circumstances, DCE 14 may be capable of clocking RD from DCE 12 into the SD path of DCE 14. However, within less than one second, the modem at DCE 14 would attempt to sample data from the modem at DCE 12 while the data is in transition. Such attempted transitional sampling results in data errors.
Further, since the ST clock of the modem of DCE 14 is 1.5 Hz faster than that of the modem of DCE 12, one or two additional cycles of the DCE 14 clock will occur per second. In view of the assumed stability of the two clocks, however, even if the clocks drift, the ST clock of DCE 14 will still be faster than the RT clock of DCE 12. Thus, it is likely that DCE 14 will always be faster than DCE 12. Nonetheless, at times, the RT and ST clocks may "walk" backwards and forwards with respect each other. Under such circumstances data errors are even more frequent than above noted.
Accordingly, it is known in the prior art to utilize data buffering by a FIFO (first in first out register), in order to hold off clocking errors for a predetermined amount of time.
A passive DTE, however, is incapable for compensating for such frequency mismatch. Data buffering is accordingly needed.
A known device capable of performing the required buffering is the model 2401H Dual Elastic Buffer marketed by Telecommunications Techniques Corp. However, such a device requires internal rewiring to meet specifications of both the DTE and DCE. Moreover, the buffer included therein is only 64 bits long and is thus too short to avoid frequent underflow and overflow alarm conditions. Still further, controls for the overflow and underflow alarms are not easily accessible. Additionally, preloading of the buffer is not selectable.
For illustrative purposes, for send timing operating at 56,000 bits per second and for received timing controlled by a clock operated at 56,002 bits per second, a phase drift of 2 bits per second results. Without selectable preload, the buffer is loaded to 32 bits prior to operation. Accordingly, only 32 bits are available for phase drift. Thus, overflow occurs each 16 seconds for the above described example.
When operating with communication devices which resynchronize on under- and over-flow conditions, a maximum number of such resynchronizations may be effected for a given period of time (10 hours). For the above described example, 2,250 overflows would occur. However, the communication device may only be capable of resynchronizing 500 times during this period.
Such prior art devices are thus incapable of providing efficient and continuous data transmission.
Other known prior art devices are described in a number of patents.
Iijima, U.S. Pat. No. 4,472,803, provides a data transmission system wherein buffers are activated by a counter set to a predetermined reference value. However, such an arrangement does not apply to the types of circuits contemplated by the present invention. The '803 apparatus is used on a point-to-point (i.e. single segment) circuit for transmission of specific information which may be produced at different speeds. Thus, the apparatus does not compensate for two different clock frequencies of two separate segments of a communication network.
Haberle et al., U.S. Pat. No. 3,825,899, describes a satellite transponder communication system incorporating elastic buffering techniques to confine data to a synchronized transmission line. This apparatus, however, is specifically designed as a pre- and post-processor for interfacing data to a time domain multiple access (TDMA) device on satellite systems. Data is altered by the '899 device by addition or deletion of a selected number of bits in order to assure that data will be properly clocked out of a memory and have a valid and acceptable format, which may have a different transmission speed from that initially provided thereto. The device is accordingly unrelated to communication between two segments of a multi-segment communication network wherein constant clock phase drift or phase error may exist at the modem interfaces between the two segments.
Hanson, U.S. Pat. No. 4,484,327, identifies an interface between two data communications systems operating at different rates. A buffer is used for this purpose. This reference is intended to interface two devices operating at completely different data rates, however, such as 9,600 bps and 19,200 bps. Hanson (similarly to Haberle) inserts and deletes bits at both ends of the circuit.
Munter, U.S. Pat. No. 4,154,985, discloses an interface circuit for digital telephone facilities operating at different rates. Elastic storage circuits are utilized for coupling data signals from the two facilities. However, similarly to the '327 apparatus, the '985 device is utilized to convert data transmission rates. The disclosure does not teach how to provide ongoing communication between two segments of a system having substantially identical data transmission rates but which may be differentiated by a small error in frequency.
Markey, U.S. Pat. No. 4,009,343, discloses interface circuitry for a data communication system. Therein, synchronization is provided by a master clock data stream transmission from a local station. However, similarly to the above described '985 disclosure, the apparatus disclosed in the '343 patent is specifically designed as an interface for data channels on satellite systems and not for general communication networks. Such an arrangement is unrelated to buffering data between links in a multisegment configuration.
Still other prior art disclosures consider concepts related to the issues herein addressed. Thus, in IBM Technical Disclosure Bulletin Vol. 22, No. 10, March, 1980, there is disclosed at pages 4597-4599 an elastic buffer having an automatic shift correction capability. More particularly, a number of latches, 15, 16 and 17, control transfer of data from latches 12, 13 and 14. Load timing pulses are provided at the same frequency as Input timing pulses from the transferring system while data is transferred to the receiving system under the control of Read Request pulses generated by the receiving system. However, Read and Reset timing pulses are required at twice the rate of the Input timing pulses. Moreover, reading out of the buffer typically starts at its middle. Nonetheless, when two consecutive data loads occur positive shift information is memorized indicating that input timing is faster than output timing, and when two consecutive data reads occur negative shift information is memorized, indicating that output timing is faster than input timing. At the conclusion of a message the remaining stored data are read out, "one" data bits enter the buffer, and the control latches are preset according to the shift information to set the device in an "almost full" or "almost empty" state for the next message.
Moreover, in IBM Technical Disclosure Bulletin Vol. 23, No. 7A, December 1980, there s disclosed at pages 2888-2890 an elastic buffering technique for a satellite communication controller. The arrangement is intended to compensate for variations in the diurnal slant range between an earth station and the satellite by providing only enough buffering to accommodate the effects of the greatest expected deviation in slant range plus an additive factor to enable local synchronization with the transmit clocks. In operation, however, a receive frame timing at the receiving station is delayed, by providing the elastic buffer storage, until a delay period of delta magnitude after the earliest receive frame time has expired. The disclosure contemplates situations wherein the transmit clock and the receive clock at a given station have non-coincident frame intervals, i.e., are not in phase, but does not address a situation wherein the clock frequencies are different.
National Physical Laboratory Report DITC 38/84 of January, 1984, contemplates the use of elastic buffers for digital rings. Questions of synchronization are addressed therein. However, such synchronization appears to be related to component timing changes, rather than to compensation for different clock frequencies used to enter and withdraw data from a terminal equipment. In other words, the report appears to consider a self adapting buffer for systems controlled by a single clock, and not the multi-segment, multi-clocked systems contemplated herein.